In semiconductor devices in which a plurality of chips are connected in parallel on an external bus, as in DRAM (Dynamic Random Access Memory), there may be signal reflection by chips with an output buffer in a high impedance state (Hi-Z). Since signal quality in the external bus degrades when this type of signal reflection occurs, in a semiconductor device where a high data transfer rate is required, as in a DDR2 or DDR3 SDRAM (Synchronous DRAM), an ODT function may be provided in which an output circuit functions as a termination resistor.
When an ODT function is provided in a semiconductor device, it is not necessary to provide a termination resistor on a motherboard. As a result, it is possible to reduce the number of parts, and also to prevent signal reflection more effectively, and thus it becomes possible to improve signal quality on the external bus.
ODT operation is turned ON/OFF according to an ODT signal. Here, a period of time from the timing when the ODT signal is activated to the timing when the ODT operation is turned ON is called ODT latency (ODTL). The value of the ODTL is fixed at 2 clock cycles in a DDR2 SDRAM, but is defined as “AL+CWL−2” in a DDR3 SDRAM. This is because if the ODTL value was fixed at 2 clock cycles, turning an ODT operation ON/OFF would not be done in time when the clock cycle would shorten with improvement in clock frequency. Here, “AL” is additive latency, and indicates an advanced input cycle of a column command. “CWL” is column address strobe (CAS) write latency indicating a clock cycle from an input of a write command to an input of write data.
A DLL (Delay Locked Loop) circuit is provided in SDRAM or the like in order to generate a clock signal for timing of data output in synchronization with a clock signal inputted from outside. An ODT operation also is done in synchronization with a clock signal generated by the DLL circuit (Japanese Patent Kokai Publication No. 2007-115366A).
However, a conventional DLL circuit is in an active state when an ODT operation is activated to be performed. As a result power consumption in the conventional DLL circuit increases.